1. Field of the Invention
The present invention relates to an image data processing apparatus for processing image data in a facsimile and so on, by encoding image data read from a reading portion and by storing the resultant encoded data in a memory.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional reading device provided with an encoding circuit which is incorporated in a certain type of hardware, e.g., a facsimile. As is clear from the figure, a line memory 703 is interposed between a reading portion 701 such as a CCD and a coding portion 702 and is adapted to temporarily store data read by the reading portion.
In the above-described type of reading device, analog data is read out from the reading portion 701 for each picture element of the CCD that forms the reading portion in synchronism with a basic clock generated at a fixed timing. The reading device has the above-described configuration because, if binary data obtained by converting the analog data is directly input to the coding portion 702 which performs coding utilizing the well-known modified Huffman coding scheme (MH) or modified READ coding scheme (MR), the coding device must process data at an extremely high speed.
Further, even if such high-speed processing were to be realized, it would be very difficult to DMA transfer the coded data to an image memory 705 in a system through a system bus 704 of a general-purpose microcomputer 706 due to the time required for DMA transfer.
It has therefore been the practice to temporarily store at least the data which represents one line of an original in the line memory 703. The coding portion 702 processes encoding using the data stored in the line memory 703. In this way, even though the encoding process must be temporarily suspended to take account of the rate of DMA transfer, erasure of data which has been read can be avoided.
Thus, the conventional arrangement requires the line memory 703 to be interposed between the reading portion 701 and the coding portion 702, and this necessitates provision of an address generating circuit, a line memory selecting circuit and so on, which are used to control the line memory.
Further, since the code lengths of encoded data vary greatly since the length depends on the contents of the data read, the times required for encoding and the times required to DMA transfer the coded data differ accordingly. Thus, the drive needed for reading one line of the original assumes an intermittent form. In consequence, in order to increase the speed at which one line of the original is read, an expensive pulse motor driven by a self-started frequency must be used to feed the original.
Furthermore, since a large scale memory generally has a capacity on the order of several M bytes (millions of bytes), not all of it is disposed on the physical address space of the microcomputer, but it has a bank structure. In consequence, when data is DMA transferred over to the separate banks, the DMA operation must be suspended once in order to execute the program required to change the bank address.
Furthermore, the CPU cannot obtain access to other banks while the data is being DMA transferred to one of them.